Current Issue : January-March Volume : 2025 Issue Number : 1 Articles : 5 Articles
With the boom in artificial intelligence (AI), numerous reconfigurable convolution neural network (CNN) accelerators have emerged within both industry and academia, aiming to enhance AI computing capabilities. However, this rapid landscape has also witnessed a rise in hardware Trojan attacks targeted at CNN accelerators, thereby posing substantial threats to the reliability and security of these reconfigurable systems. Despite this escalating concern, there exists a scarcity of security protection schemes explicitly tailored to counteract hardware Trojans embedded in reconfigurable CNN accelerators, and those that do exist exhibit notable deficiencies. Addressing these gaps, this paper introduces a dedicated security scheme designed to mitigate the vulnerabilities associated with hardware Trojans implanted in reconfigurable CNN accelerators. The proposed security protection scheme operates at two distinct levels: the first level is geared towards preventing the triggering of the hardware Trojan, while the second level focuses on detecting the presence of a hardware Trojan post-triggering and subsequently neutralizing its potential harm. Through experimental evaluation, our results demonstrate that this two-level protection scheme is capable of mitigating at least 99.88% of the harm cause by three different types of hardware Trojan (i.e., Trojan within RI, MAC and ReLU) within reconfigurable CNN accelerators. Furthermore, this scheme can prevent hardware Trojans from triggering whose trigger signal is derived from a processing element (PE). Notably, the proposed scheme is implemented and validated on a Xilinx Zynq XC7Z100 platform....
In recent years, various graph computing architectures have been proposed to process graph data that represent complex dependencies between different objects in the world. The designs of the processing element (PE) in traditional graph computing accelerators are often optimized for specific graph algorithms or tasks, which limits their flexibility in processing different types of graph algorithms, or the parallel configuration that can be supported by their PE arrays is inefficient. To achieve both flexibility and efficiency, this paper proposes Grapher, a reconfigurable graph computing accelerator based on an optimized PE array, efficiently supporting multiple graph algorithms, enhancing parallel computation, and improving adaptability and system performance through dynamic hardware resource configuration. To verify the performance of Grapher, this paper selected six datasets from the Stanford Network Analysis Project (SNAP) database for testing. Compared with the existing typical graph frameworks Ligra, Gemini, and GraphBIG, the processing time for the six datasets using the BFS, CC, and PR algorithms was reduced by up to 39.31%, 35.43%, and 27.67%, respectively. The energy efficiency has also been improved by 1.8× compared to Hitgraph and 4.7× compared to ThunderGP....
A fundamental aspect in the evolution of Time-to-Digital Converters (TDCs) implemented within Field-Programmable Gate Arrays (FPGAs), given the increasing demand for detection channels, is the optimization of resource utilization. This study reviews the principal methodologies employed for implementing low-resource TDCs in FPGAs. It outlines the foundational architectures and interpolation techniques utilized to bolster TDC performances without unduly burdening resource consumption. Low-resource Tapped Delay Line, Vernier Ring Oscillator, and Multi-Phase Shift Counter TDCs, including the use of SerDes, are reviewed. Additionally, novel low-resource architectures are scrutinized, including Counter Gray Oscillator TDCs and interpolation expansions using Process–Voltage–Temperature stable IODELAYs. Furthermore, the advantages and limitations of each approach are critically assessed, with particular emphasis on resolution, precision, non-linearities, and especially resource utilization. A comprehensive summary table encapsulating existing works on low-resource TDCs is provided, offering a comprehensive overview of the advancements in the field....
Adaptive-morphology multirotors exhibit superior versatility and task-specific performance compared to traditional multirotors owing to their functional morphological adaptability. However, a notable challenge lies in the contrasting requirements of locking each morphology for flight controllability and efficiency while permitting low-energy reconfiguration. A novel design approach is proposed for reconfigurable multirotors utilizing soft multistable composite laminate airframes. These airframes show kinematically determinate morphologies corresponding to multiple minima in their elastic potential energy landscape. By varying design parameters, the methodology allows for tuning the energy landscape characteristics governing each morphology’s structural stability and reconfiguration energetics. The airframe, composed of multistable composite laminate grids, is optimized to maximize rigidity under flight loads and minimize reconfiguration work. The 130-g reconfigurable multirotor design demonstrates self-locking properties in an open and a folded configuration, enabling a 48% reduction in width-span without compromising stability during flight. Soft pneumatic actuators, actuated using a tethered compressed air supply, enable reversible reconfiguration on the ground between open and folded configurations. The design resolves the conflicting requirements of high-stiffness to lock each flight configuration and lowactuation work for reconfigurability. By exploiting soft yet multistable structures, the approach combines the stability observed in rigid-linked reconfigurable multirotors with the low-effort reconfigurability of soft multirotors, offering new methods for designing adaptive-morphology multirotors....
In industry 4.0/5.0, Smart manufacturing systems are typically complex systems that can be adjusted to deal with demand fluctuation through reconfigurable software/hardware. The emergence of digital twin as enabler technology can promote the operation efficiency of smart manufacturing systems. However, the modelling processes of digital twin of smart manufacturing systems is inefficient due to their complicated structures in general. Besides, the frequent reconfiguration of smart manufacturing systems and the differentiation among smart manufacturing systems will increase the burden of digital twin modelling. Therefore, a reconfigurable modelling method for digital twin of smart manufacturing systems is proposed in this paper. First, a reconfigurable modelling framework based on open architecture is proposed to provide basic model scenario for digital twin of smart manufacturing systems. Second, the reconfiguration of digital twin is elaborated from three dimensions, including reconfigurable virtual model, reconfigurable mapping, and reconfigurable scene. Finally, a case study is given to demonstrate the effectiveness of the proposed method....
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